2011 Workshop on

Compact Modeling

   

Xing Zhou Professor Nanyang Technological University, Singapore

Symposium Sessions
	Tuesday June 14
4:00	Italian Trade Commission Reception - Nanotech booth 1607, Cleantech booth 707
4:00	Innovation Showcase & Poster Session - Reception (4:00 - 6:00)
	Wednesday June 15
8:30	Workshop on Compact Modeling 1
10:30	Workshop on Compact Modeling 2
1:30	Workshop on Compact Modeling 3
4:00	Workshop on Compact Modeling 4
4:00	Piemonte Agency For Investments, Export And Tourism Reception - Nanotech booth 1607, Cleantech booth 707
4:00	Innovation Showcase & Poster Session - Reception (4:00 - 6:00)
	Thursday June 16
8:30	Workshop on Compact Modeling 5
10:30	Workshop on Compact Modeling 6
1:30	Workshop on Compact Modeling 7
4:00	Workshop on Compact Modeling 8
5:00	TechConnect Closing Networking, Partnering & Investment Reception (3rd Floor, Boylston Hallway)
Symposium Program
	Tuesday June 14
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4:00	Italian Trade Commission Reception - Nanotech booth 1607, Cleantech booth 707	Expo Hall
Back to Top
4:00	Innovation Showcase & Poster Session - Reception (4:00 - 6:00)	Expo Hall
	Wednesday June 15
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8:30	Workshop on Compact Modeling 1	Room 201
	Session chair: Xing Zhou, Nanyang Technological University, Singapore
8:30	UF “Compact” Models: A Historical Perspective (invited presentation) J.G. Fossum, University of Florida, US
9:00	Complete Surface-Potential Modeling Approach Implemented in the HiSIM Compact Model Family for Any MOSFET Type (invited presentation) M. Miura-Mattausch, M. Miyake, H. Kikuchihara, U. Feldmann, S. Amakawa, H.J. Mattausch, Hiroshima University, JP
9:30	Towards a Scalable EKV Compact Model Including Ballistic and Quasi-Ballistic Transport (invited presentation) C.C. Enz, A. Mangla, J.-M. Sallese, EPFL, CH
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10:30	Workshop on Compact Modeling 2	Room 201
	Session chair: Mitiko Miura-Mattausch, Hiroshima University, JP
10:30	Compact Models for sub-22nm MOSFETs (invited presentation) Y.S. Chauhan, D. Lu, S. Venugopalan, T. Morshed, M.A. Karim, A. Niknejad, C. Hu, University of California Berkeley, US
11:00	Xsim: An Unified Compact Model for Bulk/SOI/DG/GAA MOSFETs (invited presentation) X. Zhou, Nanyang Technological University, SG
11:30	Compact Subthreshold Modeling of Rectangular Gate and Trigate MOSFETs (invited presentation) T.A. Fjeldly, U. Monga, Norwegian University of Technology, NO
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1:30	Workshop on Compact Modeling 3	Room 201
	Session chair: Christian Enz, EPFL, CH
1:30	Trends and Challenges in Compact Modeling – a Foundry Supplier’s Perspective (invited presentation) S-W. Lee, Semiconductor Manufacturing Internation (Shanghai) Corp., CN
2:00	MOSFET threshold voltage: definition, extraction, and applications (invited presentation) M.B. Machado, O. Siebel, M.C. Schneider, C. Galup-Montoro, Federal University of Santa Catarina, BR
2:30	3D Analytical Modeling of Triple-Gate MOSFET structures (invited presentation) B. Iñiguez, R. Ritzenthaler, F. Lime, Universitat Rovira i Virgili, ES
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4:00	Workshop on Compact Modeling 4	Room 201
	Session chair: Tor Fjeldly, Norwegian University of Technology, NO
4:00	HiSIM-DG for Extracting Statistical Variations of Measured I-V Characteristics Y. Shintaku, Hiroshima University, JP
4:20	Modeling of the impurity-gradient effect in high-voltage MOSFETs Y. Maekawa, K. Fukushima, A. Tanaka, H. Kikuchihara, M. Miyake, H.J. Mattausch, M. Miura-Mattausch, Hiroshima University, JP
4:40	Charge Partition in Lateral Nonuniformly-Doped Transistor J. Zhang, X. Zhou, G. Zhu and S. Lin, Nanyang Technological University, SG
5:00	Comparison and insight into long-channel MOSFET drain current models L. Zhang, Peking University, CN
5:20	Analytic potential model for asymmetricunderlap gate-all-around MOSFET S. Wang, Peking University, CN
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4:00	Piemonte Agency For Investments, Export And Tourism Reception - Nanotech booth 1607, Cleantech booth 707	Expo Hall
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4:00	Innovation Showcase & Poster Session - Reception (4:00 - 6:00)	Expo Hall
	Thursday June 16
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8:30	Workshop on Compact Modeling 5	Room 201
	Session chair: Mansun Chan, HKUST, HK
8:30	Hardware accelerated interconnect capacitance extractor for VLSI design (invited presentation) N. Arora, Silterra Malaysia Sdn. Bhd., US
9:00	High-Voltage MOSFET Compact Modeling (invited presentation) E. Seebacher, austriamicrosystems AG, AT
9:30	Modeling of High Voltage Devices for ESD Event Simulation (invited presentation) Y. Zhou, J. Salcedo, J.-J. Hajjar, Analog Devices, Inc., US
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10:30	Workshop on Compact Modeling 6	Room 201
	Session chair: Narain Arora, Silterra Malaysia Sdn. Bhd.
10:30	A Phase-Change Random Access Memory Model for Circuit Simulation (invited presentation) M. Chan, HKUST, HK
11:00	Modeling Strategies for Flash Memory Devices (invited presentation) A. Padovani, L. Larcher, P. Pavan, Università di Modena e Reggio Emilia, IT
11:30	A Universal Memory Model for Design Exploration (invited presentation) C.-C. Wang, Y. Cao, Arizona State University, US
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1:30	Workshop on Compact Modeling 7	Room 201
	Session chair: Yu Cao, Arizona State University, US
1:30	Process Variability Modeling for VLSI Circuit Simulation (invited presentation) S.K. Saha, SuVolta, Inc., US
2:00	A Fully Anlytical Model for Carbon Nanotube FETs including Quantum Capacitances and Electrostatics (invited presentation) L. Wei, D.J. Frank, L. Chang, H.-S.P. Wong, Massachusetts Institute of Technology, US
2:30	Single-walled Carbon Nanotube (CNT) Field Effect Transistor Device Modeling H. Abebe, E. Cumberbatch, USC/ISI, US
2:50	Hot-Carrier-Induced Current Degradation in Deep Sub-Micron MOSFETs from Subthreshold to Strong Inversion Region L. Shihuan, Nanyang Technology University, SG
3:10	Drain Induced Barrier Lowering (DIBL) Effect on the Intrinsic Capacitances of Nano-Scale MOSFETs M.A. Karim, S. Venugopalan, Y.S. Chauhan, D. Lu, A. Niknejad, C. Hu, University of California at Berkeley, US
3:30	Characterization and Modeling of Metal Finger Capacitors N. Lu, R. Booth, D. Daley, E. Thompson, C. Putnam, IBM, US
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4:00	Workshop on Compact Modeling 8	Room 201
	Session chair: Samar Saha, Suvolta, Inc.
4:00	Analytical Solutions to Model the Line Edge Roughness and its Effect on Subthreshold Behavior of DG FinFETs U. Monga, T.A. Fjeldly, Norwegian University of Science and Technology, and University Graduate Center (UNIK), NO
4:20	Modeling Bias Stress Effect on Threshold Voltage for Amorphous Silicon Thin-Film Transistors C-H Shen, National Chiao Tung University, TW
4:40	The accurate Electro-Thermal Model of Merged SiC PiN Schottky Diodes M. Zubert, L. Starzak, G. Jablonski, M. Napieralska, M. Janicki, A. Napieralski, Technical University of Lodz, PL
5:00	The Application of RESCUER Software to Modelling of Coupled Problems in Modern Devices M. Zubert, A. Napieralski, Technical University of Lodz, PL
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5:00	TechConnect Closing Networking, Partnering & Investment Reception (3rd Floor, Boylston Hallway)	Boylston Hallway

Synopsis

Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design over the past decades, and are playing an ever increasingly important role in the nanometer system-on-chip (SOC) era.  As the mainstream MOS technology is scaled into the nanometer regime, development of a truly physical and predictive compact model for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge.

Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together. The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development and deployment, within the main theme - compact models for circuit simulation, which are largely categorized into the following groups:

• Intrinsic Models
  • Bulk MOSFET
  • SOI MOSFET (partial-/full-depletion)
  • Multiple-Gate FET (DG/TG/GAA)
  • High-Voltage/LDMOS
  • Thin-Film Transistor (TFT)
  • Schottky-Barrier/Tunneling FET (SB-FET/TFET)
  • Bipolar/Junction (BJT/HBT/SiGe/JFET)
  • RF/noise
• Extrinsic/Interconnect Models
  • Parasitic elements
  • Passive device
  • Diode
  • Resistor
  • ESD
  • Interconnect
• Atomic/Quantum Models
  • Ballistic device
  • Carbon-Nanotube (CNFET)
  • Organic FET
• Statistical Models
  • Statistical/variability
  • Reliability/hot carrier
  • Numerical/TCAD/table-based
• Multi-Level Models
  • Subcircuit model
  • Gate/block model
  • Behavioral model
• Model Extraction and Interface
  • Parameter extraction and optimization
  • Model-simulator interface
  • Model standardization

Invited Speakers

Invited speakers from all over the world are listed below:

• Narain Arora, Silterra, Malaysia
• Yu Cao, Arizona State University, USA
• Mansun Chan, Hong Kong University of Science and Technology, Hong Kong
• Christian Enz, Swiss Center for Electronics and Microtechnology, Switzerland
• Tor Fjeldly, Norwegian University of Science and Technology, Norway
• Jerry Fossum, University of Florida, USA
• Carlos Galup-Montoro, Universidade Federal de Santa Catarina, Brazil
• Chenming Hu, University of California at Berkeley, USA
• Benjamín Iñíguez, Universitat Rovira i Virgili, Spain
• Shiuh-Wuu Lee, SMIC, China
• Mitiko Miura-Mattausch, Hiroshima University, Japan
• Paolo Pavan, Università di Modena e Reggio Emilia, Italy
• Samar Saha, SuVolta, USA
• Ehrenfried Seebacher, Austriamicrosystems AG, Austria
• Philip Wong, Stanford University, USA
• Paul Zhou, Analog Devices, USA
• Xing Zhou, Nanyang Technological University, Singapore

10^th Anniversary CDROM

There will be a special CDROM collection of 2002 — 2011 WCM papers, especially the valuable inaugural WCM 2002 volume.

Topics & Application Areas

• Intrinsic Models: Bulk MOSFET
• Intrinsic Models: SOI MOSFET (partial-/full-depletion)
• Intrinsic Models: Multiple-Gate FET (DG/TG/GAA)
• Intrinsic Models: High-Voltage/LDMOS
• Intrinsic Models: Thin-Film Transistor (TFT)
• Intrinsic Models: Schottky-Barrier/Tunneling FET (SB-FET/TFET)
• Intrinsic Models: Bipolar/Junction (BJT/HBT/SiGe/JFET)
• Intrinsic Models: RF/noise
• Extrinsic/Interconnect Models: Parasitic elements
• Extrinsic/Interconnect Models: Passive device
• Extrinsic/Interconnect Models: Diode
• Extrinsic/Interconnect Models: Resistor
• Extrinsic/Interconnect Models: ESD
• Extrinsic/Interconnect Models: Interconnect
• Atomic/Quantum Models: Ballistic device
• Atomic/Quantum Models: Carbon-Nanotube (CNFET)
• Atomic/Quantum Models: Organic FET
• Statistical Models: Statistical/variability
• Statistical Models: Reliability/hot carrier
• Statistical Models: Numerical/TCAD/table-based
• Multi-Level Models: Subcircuit model
• Multi-Level Models: Gate/block model
• Multi-Level Models: Behavioral model
• Model Extraction and Interface: Parameter extraction and optimization
• Model Extraction and Interface: Model-simulator interface
• Model Extraction and Interface: Model standardization
• Other

 

Presentation Slides

Contributed presentation slides. (Click on each  to download the PDF file.  © Copyright of the PDF files belongs to the respective contributors.)

Download and save the entire ZIP file of presentation slides (33.3MB)
C. Enz, A. Mangla, J.-M. Sallese, Towards a Scalable EKV Compact Model Including Ballistic and Quasi-Ballistic Transport
M.B. Machado , O.F. Siebel, M.C. Schneider, C. Galup-Montoro, MOSFET Threshold Voltage: Definition, Extraction, and Applications
H. Abebe, E. Cumberbatch, Electrostatic Single-walled Carbon Nanotube (CNT) Field Effect Transistor Device Modeling
J.G. Fossum, UF “Compact” Models: A Historical Perspective
J. Zhang, X. Zhou, G. Zhu, S. Lin, Charge Partition in Lateral Nonuniformly-Doped Transistor
K.C. Kwong, M. Chan, A Phase-Change Random Access Memory Model for Circuit Simulation
M. Miura-Mattausch, M. Miyake, H. Kikuchihara, U. Feldmann, H. J. Mattausch, Complete Surface-Potential Modeling Approach Implemented in the HiSIM Compact Model Family for Any MOSFET Type
M. Zubert, L. Starzak, G. Jablonski, M. Napieralska, M. Janicki, A. Napieralski, The Accurate Electro-Thermal Model of Merged SiC PiN Schottky Diodes
M. Zubert, A. Napieralski, The Application of RESCUER Software to Modelling of Coupled Problems in Modern Devices
N. Lu, R. Booth, D. Daley, E. Thompson, C. Putnam, Characterization and Modeling of Metal Finger Capacitors
S. Lin, X. Zhou, Z. Chen, M.K. Srikanth, J. Zhang, Hot-Carrier-Induced Current Degradation in Deep Sub-Micron MOSFETs from Subthreshold to Strong Inversion Region
S. Saha, Process Variability Modeling for VLSI Circuit Simulation
T. A. Fjeldly, U. Monga, Compact Isomorphic Modeling of Rectangular Gate and Trigate MOSFETs
U. Monga, T. A. Fjeldly, Analytical Solutions to Model the Line Edge Roughness and Its Effect on Subthreshold Behaviour of DG FinFETs
X. Zhou, Xsim: A Unified Compact Model for Bulk/SOI/DB/GAA MOSFETs
K. Sutaria, C-C Wang, Y.K. Cao, A Universal Memory Model for Design Exploration
Y.S. Chauhan, D.D. Lu, S. Venugopalan, M.A. Karim, A. Niknejad, C. Hu, Compact Models for sub-22nm MOSFETs
Y.P. Zhou, J.A. Salcedo J.-J. Hajjar, Modeling of High Voltage Devices for ESD Event Simulation in SPICE

Web Site Archive

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• WCM 2006
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• WCM 2002

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