TechConnect World 2016
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2016 Workshop on

Compact Modeling

WCM 2016

WCM - Compact Modeling

Symposium Chair

Xing ZhouXing Zhou
Professor
Nanyang Technological University, Singapore


Symposium Sessions

Tuesday May 24

8:30Workshop on Compact Modeling (WCM) - Water Physics, Plasmonic FETs, Ion Transport
10:30WCM - Reliability & Noise
1:30WCM - Muiti-gate/SOI/Junctionless Transistors
3:30WCM - Design Platform & PDK

Symposium Program

Tuesday May 24

8:30Workshop on Compact Modeling (WCM) - Water Physics, Plasmonic FETs, Ion TransportPotomac 3
Session chair: Xing Zhou, Nanyang Technological University, SG (bio)
8:30Experimental Verification of a Water Physics and Model in Pure Water at Thermodynamic Equilibrium and Non-Equilibrium
B. Jie, C. Sah, Xiamen University, CN
9:00Terahertz SPICE for Nanometer Scale Plasmonic Field Effect Transistors and Circuits
M. Shur, A. Gutin, T. Ytterdal, G. Aizin, Rensselaer Polytechnic Institute, US
9:30Modeling the Coupled Ion and Fluid Transport in Nano-Channels and Nanopores
L. Guo, X. Zhu, X. Zhang, Y. Liu, Q. Ran, R. Dutton, Zhejiang University, CN
10:30WCM - Reliability & NoisePotomac 3
Session chair: Bin Jie, Xiamen University, China
10:30Compact Modeling of Long-Term MOSFET Degradation for Predicting Circuits Degradation
H. Miyamoto, C. Ma, H. Tanoue, Y. Tanimoto, H. Kikuchihara, H.J. Mattausch, M. Miura-Mattausch, Hiroshima University, JP
11:00Reliability-Aware Device Modeling and Implications on Circuit Aging Simulations
L. Zhang, C. Ma, M. Chan, Hong Kong University of Science and Technology, HK
11:30A Physics Based Approach to Compact Modeling of Noise in Modern Bipolar Transistors
G. Niu, Auburn University, US
1:30WCM - Muiti-gate/SOI/Junctionless TransistorsPotomac 3
Session chair: Lining Zhang, Hong Kong University of Science and Technology, HK
1:30Modeling Independent Multi-Gate MOSFET
J.P. Duarte, S. Khandelwal, H-L Chang, Y.S. Chauhan, C. Hu, University of California, Berkeley, US
2:00Compact modeling for UTBB-FDSOI technologies: Main challenges and possible solutions
T. Poiroux, CEA-Leti, FR
2:30Modeling Methodology of GaN HEMTs for HV and HF applications
U. Radhakrishna, P. Choi, S. Lim, T. Palacios, D. Antoniadis, MIT, US
3:003-D Analytical Model for Short-Channel Triple-Gate Junctionless MOSFETs
Y. Wang, Z. Guo, Tsinghua University, CN
3:30WCM - Design Platform & PDKPotomac 3
Session chair: Ujwal Radhakrishna, MIT, USA
3:30NEEDS: Tools for Developing and Disseminating Compact Models
X. Wang, M. Lundstrom, Purdue University, US
4:00A Hybrid Process Design Kit: Towards Integrating CMOS and III-V Devices
S.B. Chiah, X. Zhou, K.E.K. Lee, C.Y. Ng, D. Antoniadis, E.A. Fitzgerald, Nanyang Technological University, SG
4:30New Elements and Features in the Process Design Kits for a FinFET Technology
N. Lu, A. Baizley, X. Guan, J. Johnson, J. McCullen, A. Ozbek, A. Rahman, H. Wang, M. Yu, C. Zemke, W. Rausch, R. Wachnik, IBM, US
5:00SPICE Compact Modeling for Design of Innovative Integrated Circuits in CEA-LETI
P. Martin, L. Lucci, M. Reyboz, J.-C. Barbe, CEA-LETI, FR

Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design over the past decades, and are playing an ever increasingly important role in the nanometer system-on-chip (SOC) era. As the mainstream MOS technology is scaled into the nanometer regime, development of a truly physical and predictive compact model for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge.

Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together. The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development and deployment, within the main theme - compact models for circuit simulation, which are largely categorized into the following groups:

  • Intrinsic Models
    • Bulk MOSFET
    • SOI MOSFET (partial-/full-depletion)
    • Multiple-Gate FET (DG/TG/GAA)
    • High-Voltage/LDMOS
    • Thin-Film Transistor (TFT)
    • Schottky-Barrier/Tunneling/Junctionless FET (SB-FET/JLFET/TFET)
    • Bipolar/Junction (BJT/HBT/SiGe/JFET)
    • HEMT (GaN/InGaP/InGaAs)
    • Non-quasi-static
    • RF
  • Extrinsic/Interconnect Models
    • Parasitic elements
    • Passive device
    • Diode
    • Resistor
    • ESD
    • Interconnect
  • Atomic/Quantum Models
    • Ballistic device
    • Carbon-Nanotube/Graphene FET (CNFET/GFET)
    • Organic FET
  • Statistical Variability/Reliability/Noise Models
    • Statistical variability
    • Reliability/hot carrier
    • Mismatch
    • Noise
  • Multi-Level Models
    • Subcircuit model
    • Gate/block model
    • Behavioral model
    • Numerical/TCAD/table-based
  • Model Extraction and Interface
    • Parameter extraction and optimization
    • Model-simulator interface
    • Model standardization
    • Model development platform
    • Verilog-A

The confirmed invited speakers are listed below:

  • Dimitri Antoniadis and Ujwal Radhakrishna, Massachusetts Institute of Technology, USA
  • Mansun Chan and Lining Zhang, Hong Kong University of Science and Technology, Hong Kong
  • Siau Ben Chiah, Nanyang Technological University, Singapore
  • Robert Dutton and Yang Liu, Stanford University, USA
  • Chenming Hu and Juan Pablo Duarte, University of California at Berkeley, USA
  • Binbin Jie and Chihtang Sah, Xiamen University, China
  • Ning Lu, IBM, USA
  • Mark Lundstrom and Xufeng Wang, Purdue University, USA
  • Patrick Martin, LETI, France
  • Mitiko Miura-Mattausch, Hiroshima University, Japan
  • Guofu Niu, Auburn University, USA
  • Thierry Poiroux, CEA, France
  • Michael Shur, Rensselaer Polytechnic Institute, USA
  • Yan Wang, Tsinghua University, China

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