M. Zubert, T. Raszkowski, M. Janicki, A. Samson, M. Jankowski, A. Napieralski*Lodz University of Technology,Poland*

Keywords: dual-phase-lag, DPL, Fourier-Kirchhoff, FinFET, thermal model

Summary:

The accurate thermal modelling of nanoscale chips is of vital importance, as heat dissipation is arguably one of the most important problems in modern integrated circuits. As the technology node is expected to continue to scale down to single nanometers, using the Fourier-Kirchhoff (F-K) heat equation for the simulation of transistors stops being a viable solution [1], because it assumes infinite heat propagation speed and instantaneous change of heat flux. More accurate simulation results can be obtained by other methods, like for example Dual-Phase-Lag (DPL) thermal model [1,2]. Therefore, in this paper we present the coupled electro-thermal simulation of multi-gate FinFET transistors, based on solving the DPL equation. Our 3D DPL thermal model of FinFET structure has been already presented in [2]. The transistor geometry was constructed using the published data on 14nm Samsung Low Power Early technology. All package layers, including silicon, all metal layers, heat spreader, heat sink, etc. are also included in the model. The parameters for each layer were estimated based on available data published by manufacturers. The simulation was performed for two adjacent transistors with the assumption that lateral boundary conditions are adiabatic, in other words a vertical slice of the chip package is simulated. The local no-mesh FDM together with variable order Gear's method are used to solve PDEs [3]. The dedicated 3-D solver has been developed for this purpose. This software will be presented using a simple logic gate as-well-as the cadence GDSII data import possibility. References: [1] Janicki, M.; De Mey, G.; Zubert, M.; Napieralski, A., "Comparison of fourier and non-fourier heat transfer in nanoscale semiconductor structures," in 30th Annual Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), pp.202-206, 9-13 March 2014 [2] M.Zubert, M. Janicki, Tomasz Raszkowski, A. Napieralski, "The Thermal Model of Fin-FET Transistor”, to be presented at 21st International Workshop on Thermal Investigation of ICs and Systems (THERMINIC), 30 Sept.- 2 Oct. 2015, Paris, France [3] M. Zubert, M. Napieralska and A. Napieralski, “Rescuer—the new solution in multidomain simulations”, Microelectronics Journal, 31(11):945-954, 2000 [4] S. Sinha, B. Cline, G. Yeric, V. Chandra, and Y. Cao, “Design benchmarking to 7nm with FinFET predictive technology models”, In Proc. of Int'l Symp. on Low Power Electronics and Design (ISLPED), 2012