R. Senegor, A. Adesida, C. Zhou, A.A. Vyas, P. Wang, C.Y. Yang
Santa Clara University,
Keywords: graphene, carbon, nanotube
Summary:Continuous downward scaling in silicon integrated circuit technology into the sub-20 nm regime has created critical challenges in chip manufacturing, among them, reliability and performance of on-chip interconnects . Current interconnect materials, Cu and W, face increased reliability challenges in the nanoscale as a result of electromigration failures at high current densities. Materials such as nanocarbons, metal silicides, and metallic nanowires  are being considered as potential replacements for Cu and W in via interconnects, due to their superior electrical and mechanical properties, as well as much higher current-carrying capacities. A low-resistance three-dimensional all-carbon interconnect structure can potentially be realized utilizing the strong C-C sp2 bonding in carbon nanotubes (CNTs) and graphene, by fabricating the growth of CNTs directly on one or few layers of graphene (MLG). While such growth has been demonstrated [2-3], the CNT/graphene interfacial nanostructure and how it impacts the electrical properties of the 3-D structure are far from being understood. Our test structure consists of MLG grown by annealing a Ni thin film in H2/CH4 ambient inside a low-pressure PECVD chamber, before being transferred onto an oxide-covered silicon substrate. Vertically aligned CNTs are then grown on the transferred MLG in a PECVD system using a similar recipe as in our previous work on CNT vias , resulting in a 3-D all-carbon interconnect structure. Scanning and transmission electron microscopy images reveal excellent CNT alignment and interfacial nanostructure comparable to the CNT-Cr interface in CNT via . Current-voltage characteristics of the 3-D test structure are obtained using a nanoprober in situ in the SEM chamber. The resulting resistance is compared with those of sub-100 nm linewidth CNT vias . Our results demonstrate the feasibility of fabricating a 3-D CNT/graphene device, which can serve as the building block for all-carbon interconnects. Enhanced understanding of the relationship between interfacial nanostructure and device resistance can lead to eventual functionalization of contacts between CNT vias and a graphene-based planar interconnect network in the most advanced technology nodes.  International Technology Roadmap for Semiconductor 2014 Edition, available online at http://www.itrs2.net/itrs-reports.html.  R. Rao, G. Chen, L.M.R. Arava, K. Kalaga, M. Ishigami, T.F. Heinz, P.M. Ajayan, and A.R. Harutyunyan, Scientific Reports 3, 1891 (2013).  K. Kumar, Y-S. Kim, X. Li, J. Ding, F.T. Fisher, and E-H. Yang, Chemistry of Materials 25, 3874 (2013).  C. Zhou, A.A. Vyas, P. Wilhite, P. Wang, M. Chan, and C.Y. Yang, IEEE Electron Device Letters 36, 71 (2015).