Gilles S.C. Lamant holds an engineering degree (~MsEE) from ESIEE (Ecole Superieure d’ingénieurs en Electronique et Electrotechnique), Paris, France. After holding several customer facing positions in Cadence Services organization, with a focus on custom (analog) design, in multiple countries (US, Japan, Russia), he joined the Virtuoso Custom Platform R&D team in 2003. His interests are usually found below Metal1, at the device level. He pioneered the Virtuoso FinFET implementation, and has been focussing on the photonics layers for the past few years. In that capacity, he has led the partnership between Cadence and other eco-system companies driving the integration and co-development of the EPDA (Electronics-Photonics Design Automation) platform around the Virtuoso ® Platform.