S. Yang, S. Jung, S. Park, D. Kim, H. Ban, D. Song, B. Choi
Samsung Electronics Co. / Sungkyunkwan University,
Korea
Keywords: DRAM, refresh, retention time, electric field, leakage, buried channel array transistor
Summary:
Reducing the leakage current is one of the most important factors to improve DRAM refresh characteristics. And the gate-induced drain leakage current (GIDL) and the gate-induced junction leakage current (GIJL) are known to be major cell leakage current. In this study, we propose an effective structural method to decrease both GIDL and GIJL at once using the optimized fin profiles of Buried Channel Array Transistor (BCAT). We first conduct a simulation study to analyze the electric field distribution. Each time the fin height was lowered, we could see the simulation results of the electric field decreasing linearly. And we performed experiments from a reliable mass production fab using 20nm DRAM process. The GIDL and GIJL are measured from cell arrays in a test element group (TEG). We found, from our optimized fin profile, both GIDL and GIJL were reduced by 9.8% and 22.3%, respectively. The retention time and other refresh characteristics according to the fin profiles will be further discussed from a whole device standpoint.