A. Zhang, C. Li, Y. He, J. Liu, X. He, G. Ma, J. Pan, J. He, G. Hu
Peking University Shenzhen Institute and PKU-HKUST Shenzhen-Hong Kong Institution,
China
Keywords: capacitance model, 3-D terminal, terminal fringe, electric field decomposition, 3-D interconnect, TSV process
Summary:
In this paper, a parasitic capacitance model for a finite single three-dimensional (3-D) wire above an infinite plate in the nano-scale 3-D integrated circuit application is developed based on electric field decomposition (EFD). The capacitance components at wire ends, i.e., the 3-D terminal and terminal fringe capacitance, are considered by the 3-D electric field analysis. Verified by extensive COMSOL simulations, the model can accurately predict parasitic capacitance for a wide range of 3-D BEOL wire dimensions in the beyond 28nm CMOS process technology.