J. Modasiya, M. Liehr, N. Cady
University at Albany,
United States
Keywords: ReRAM, crossbar arrays, in-memory computing, multiplier
Summary:
The conventional von Neumann computing architecture requires memory and logic units to be physically separated. As computers and data size have scaled, this physical separation has created the so-called von Neumann bottleneck, where data transfer between logic and memory units is the primary limiting factor for speed and efficiency. Emerging non-volatile memories have the potential to resolve this bottleneck by enabling logic and other computing functions within or directly adjacent to memory. One of the leading candidates is resistive random access memory (ReRAM) due to its high read and write speeds, non-volatility, back-end of line (BEOL) fabrication compatibility, storage density, and scalability. This makes ReRAM a strong contender to complement or even replace SRAM, DRAM, and NAND flash memories. Each ReRAM cell consists of a metal-insular-metal device stack in which the insulating material’s conductance can be modified through initial electroforming and subsequent voltage biasing. Transition metal oxides have been heavily investigated as the switching material in ReRAM, due to the ability to generate and manipulate oxygen defects (vacancies) within the material. Oxygen vacancies within such oxides can be manipulated using an applied electric field to vary conductance. Using 65 nm CMOS transistors fabricated on a 300 mm wafer as a baseline process, our group has integrated 8x8 and 64x64 arrays of ReRAM devices in a 1 transistor 1 ReRAM (1T1R) configuration. To demonstrate the potential of in-memory, non-Von Neumann computing, 8x8 ReRAM arrays were programmed to implement 2-bit and 3-bit multiplier functionality, based on current percolation through the arrays. For a 2-bit multiplier, each column was assigned either a gate input of 0 or 1 using a combination of two Boolean variables (2-bit) while the 3-bit multiplier used a combination of three Boolean variables (3-bit). These array-based multipliers were then tested by applying variable inputs and comparing measured current outputs to the expected truth tables. Initial experiments yielded excellent agreement between measured vs. expected current outputs for the 3-bit multiplier design, while results from the 2-bit multiplier were highly dependent upon the conductance level of the ReRAM cells within the array. Ongoing efforts are focused on the optimization of the multiplier design and the selection of optimal ReRAM conductance levels to improve multiplier performance. While 3-bit multipliers based on traditional CMOS can require between 150-200 transistors, in-memory computing of 3-bit multiplier operations can be implemented fully within an 8x8 (64 cell) ReRAM array, demonstrating the potential of both area-efficiency and computational efficiency.