C.N.K. Choudary, C.T. Siddanth
Amrita Vishwa Vidyapeetham,
India
Keywords: UART, VLSI design, low-power, IoT, dynamic voltage scaling, adaptive baud rate, FPGA validation
Summary:
The Universal Asynchronous Receiver-Transmitter (UART) is a ubiquitous serial communication interface utilized in IoT and embedded systems due to its simplicity and effectiveness. However, traditional UART designs face significant challenges in addressing the stringent requirements of power efficiency, resource optimization, and communication reliability demanded by modern IoT devices. To overcome these limitations, this paper proposes a novel VLSI-based architecture for a low-power UART module, specifically designed for resource-constrained and energy-sensitive IoT applications. The proposed UART architecture introduces a suite of advanced power-saving techniques. Dynamic Voltage Scaling (DVS) dynamically adjusts the operating voltage of the circuit based on workload intensity, thereby reducing active power consumption. An adaptive baud rate control mechanism optimizes the data transmission rate depending on the system requirements, enabling efficient utilization of bandwidth and further lowering power dissipation during low-traffic states. Power-gating strategies are implemented to deactivate inactive functional blocks during idle periods, effectively minimizing leakage currents and enhancing overall energy efficiency. To improve communication robustness, the design incorporates a lightweight error detection and correction mechanism. This module uses a cyclic redundancy check (CRC) for error detection and simple Hamming code-based correction to ensure reliable data transmission even in noisy environments, commonly encountered in IoT applications. Additionally, a modular and scalable design framework is employed, enabling the UART to support multi-protocol communication, including SPI and I2C, and facilitating seamless integration with diverse system-on-chip (SoC) architectures. The design will be validated through rigorous simulation using ModelSim and synthesized on a Xilinx Artix-7 FPGA. Key performance metrics, such as power consumption, area utilization, data throughput, and error resilience, will be benchmarked against conventional UART designs. Preliminary analysis suggests substantial improvements in energy efficiency, achieving up to a 30% reduction in power consumption, while maintaining high data integrity and throughput. This work aims to establish a comprehensive design methodology for next-generation communication modules, addressing critical challenges in energy-efficient, reliable data transfer for IoT and embedded systems. The proposed architecture is positioned as a scalable and future-ready solution for sustainable electronics, paving the way for enhanced performance in ultra-low-power applications across diverse IoT use cases.