J.J. Modasiya, R. Mathkari, K. Beckmann, N.C. Cady
University at Albany,
United States
Keywords: resistive RAM, non-volatile memory, tantalum oxide, memory window
Summary:
The conventional von Neumann computing architecture requires memory and logic units to be physically separated. As processor capability and memory size have scaled, this physical separation has created the so-called “von Neumann bottleneck”, where data transfer between logic and memory units significantly limits maximum speed and efficiency. Emerging non-volatile memories have the potential to resolve this bottleneck by enabling logic and other computing functions within or directly adjacent to memory. One of the leading candidates is resistive random-access memory (ReRAM) due to its high read and write speeds, non-volatility, back-end of line (BEOL) fabrication compatibility, storage density, and scalability. This makes ReRAM a strong contender to complement or even replace SRAM, DRAM, and NAND flash memories. Each ReRAM cell consists of a metal-insular-metal device stack in which the insulating material’s conductance can be modified through initial electroforming and subsequent voltage biasing. Transition metal oxides have been heavily investigated as the switching material in ReRAM, due to the ability to generate and manipulate oxygen defects (vacancies) within the material. Oxygen vacancies within such oxides can be manipulated using an applied electric field to vary conductance. One of the primary challenges with ReRAM is relatively high leakage current even when switched to an OFF state. To mitigate this challenge, a novel multi-layer switching stack was proposed and electrical operating conditions were optimized to reduce conductance in the OFF state without affecting other characteristics. To accomplish this, near-stoichiometric TaOx films were deposited on TiN electrodes, followed by the deposition of sub-stoichiometric TaOx through reactive sputtering. The thickness of the sub-stoichiometric film was varied to optimize overall device performance. A tantalum oxygen exchange layer (OEL) was also deposited on top of the switching layer followed by an iridium capping layer to prevent oxidation of the top electrode due to oxygen diffusion during switching. Electrical characterization revealed that bi-layer devices with a 5 nm sub-stoichiometric TaOx layer exhibited the best switching characteristics along with low electroforming voltages ~ 2.5 V. The initial laboratory-scale fabrication process was then transferred to 300 mm wafer scale. To increase the memory window via reduction of conductance during OFF state, lower compliance currents were implemented during the forming and switching cycles. Using a compliance current of 125 uA resulted in high resistance state (HRS) and low resistance state (LRS) values of ~ 86 kΩ and 10 kΩ, respectively, whereas 35 uA compliance resulted in the highest HRS and LRS values of ~ 500 kΩ and 48 kΩ, respectively. Due to lower compliance currents, we see a slightly increased memory window while also reducing leakage significantly in the OFF (HRS) state. Lower operating currents also lead to lower reset voltage during cycling, with -1.25 Vreset for 125 uA, to -0.85 Vreset for 35 uA.