J. Liberkowski
VSens Inc.,
United States
Keywords: High-Temperature Superconducting, Integrated Circuits
Summary:
Janusz Liberkowski VSens Inc. 2060 Forest Ave., Suite 200, San Jose, CA 95128 Janusz@VSens.us Project Title: Programmable Two-Layer Interconnect Architecture for High-Temperature Superconducting Quantum Integrated Circuits The scalability of superconducting quantum integrated circuits is increasingly constrained by interconnect complexity, fabrication reliability, and material incompatibilities. While current quantum hardware architectures largely resemble conventional transistor-based integrated circuits, their reliance on complex multilayer interconnect stacks introduces critical challenges, particularly when high-temperature superconductors (HTS) are employed. This project proposes a fundamentally new programmable interconnect architecture that enables dynamic, scalable connectivity using only two conductive layers, addressing a key bottleneck in the advancement of superconducting quantum technologies. High-temperature superconductors are predominantly ceramic cuprate compounds whose superconducting behavior depends on a precisely controlled layered crystal structure. Although these materials enable operation at elevated cryogenic temperatures, typically between 40 K and 77 K, they are intrinsically brittle and highly sensitive to mechanical strain and thermal contraction. As a result, the fabrication of reliable superconducting traces, vias, and multilayer interconnects remains a major unresolved challenge in HTS-based systems. These limitations hinder yield, scalability, and long-term device reliability. The proposed research introduces a two-layer interconnect matrix in which superconducting connections are realized through engineered material layers rather than discrete superconducting traces or mechanically fragile via structures. This architecture eliminates the need for conventional multilayer routing while enabling full interconnectivity among system components. By reducing the number of conductive layers, the approach minimizes electromagnetic interference, parasitic coupling, and fabrication complexity, all of which are critical factors in quantum integrated circuits. A central innovation of this work is the incorporation of Josephson junctions at selected interconnection nodes, enabling dynamic and programmable reconfiguration of the interconnect matrix. This functionality allows real-time adjustment of coupling paths, interaction strengths, and circuit topology, providing unprecedented flexibility in quantum processor design and operation. Such reconfigurability is expected to be particularly beneficial for optimizing qubit layouts, mitigating fabrication variability, and adapting hardware configurations to specific quantum algorithms. The proposed architecture also facilitates hybrid integration of HTS-based quantum components with semiconductor-based classical control electronics on a single substrate. Operation within the 40–77 K temperature range enables efficient coexistence of superconducting circuits and cryogenic semiconductor transistors, reducing thermal gradients and simplifying system-level integration. Furthermore, the layered interconnect approach offers opportunities to mitigate thermal and electrical noise originating from external electronics. This research will advance fundamental understanding of superconducting interconnect architectures while providing a scalable pathway toward large-scale, reliable quantum integrated circuits. The expected outcomes include new design principles for HTS-compatible interconnects, experimentally validated programmable interconnection schemes, and a foundation for future hybrid quantum–classical computing platforms.