Scaling Chiplet Integration Through Advances in Printed Interconnects

This research develops scalable printed redistribution layers to interconnect silicon chiplets. Using precision high-resolution techniques we demonstrate customizable 2μm lines/spaces, <1μm overlay accuracy, and reliable routing to enable heterogeneous integration. The innovations in cost-effective dense interconnects promise to revolutionize high-volume chiplet production for AI, computing, 5G, and more.

Generative AI Requirements Development

A database and AI engine to assist government agencies and the defense industrial base in writing more effective requirements to reduce cost overruns and schedule delays.

OPERA - Operational Process Efficiency and Resource Analytics

Our technology transforms 2D engineering drawings into 3D digital models with ease. It streamlines the creation of prototypes and production-ready parts, enhancing training and visualization for technicians via AR/VR, and makes complex processes more understandable and efficient.