With passage of the 2022 CHIPS for America Act, the US government is making a $50 billion investment to catalyze long-term growth in the domestic semiconductor industry in support of US national and economic security. A significant portion of this funding - $11 billion – goes towards R&D initiatives to create a network of innovation in the US semiconductor ecosystem.
This symposium will focus on 3 target areas identified as critical to the R&D initiatives:
*This symposium gathers experts to discuss research challenges and opportunities associated with the recently passed CHIPS act, but it is not an official activity by or related to the US CHIPS office.
Back to Top ↑2023 Symposium Sessions |
| 1:30 | CHIPS: Current Challenges and New Solutions to Boost Domestic Chips Manufacturing I |
| Tuesday June 20 |
| 10:30 | CHIPS: Keynotes |
| 1:30 | CHIPS: Advanced Metrology to Ensure Success for Next Generation Semiconductors |
| Wednesday June 21 |
| 9:00 | CHIPS: Advances in Packaging for New Chips Innovation |
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2023 Symposium Program |
| Monday June 19 |
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| 1:30 | CHIPS: Current Challenges and New Solutions to Boost Domestic Chips Manufacturing I | Chesapeake 3 |
| Session chair: Joe Kline, National Institute of Standards & Technology, US |
| 1:30 | Mitigating challenges in high resolution imaging and electrical failure analysis for advanced semiconductor devices
S. Basu, Zeiss, US |
| 1:55 | Critical Materials for Critical Goods: Rebuilding the Microelectronics Industrial Base
A.N. Caruso, Midwest Microelectronics Collective, US |
| 2:15 | Semiconductor manufacturing for meta-optics
W.T. Chen, SNOChip, US |
| 2:40 | Vulnerability of In-Memory Compute to Hardware Trojans: A Case Study using Two-dimensional Memtransistor
A. Wali, H. Ravichandran, S. Das, Pennsylvania State University, US |
| 3:00 | Accelerate time to market of semiconductor industry using AI software platform dedicated to data analytics for metrology and defectivity
J. Foucher, S. Martinez, H. Ozdoba, J. Baderot, O. Cru, T. Ziraoui and S. Girard, Pollen Metrology, FR |
| 3:20 | A Novel Photonic Switching Device
K. Sampayan, S. Sampayan, Opcondys, Inc., US |
| Tuesday June 20 |
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| 10:30 | CHIPS: Keynotes | National Harbor 6 |
| Session chair: Alex Norman, Princeton University, US |
| 10:30 | Whole-of-Government efforts to support microelectronics R&D
L.E. Friedersdorf, Office of Science and Technology Policy, US |
| 10:55 | The role of academia in the future of semiconductor manufacturing
D. Lopez, Pennsylvania State University, US |
| 11:20 | CHIPS for America Research and Development
M. Dowell, National Institute of Standards and Technology, US |
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| 1:30 | CHIPS: Advanced Metrology to Ensure Success for Next Generation Semiconductors | National Harbor 6 |
| Session chair: Alex Norman, Princeton University, US |
| 1:30 | In-Line Metrology Requirements and Needs for Leading Edge Technology
D. Schmidt, IBM Research, US |
| 1:55 | Solutions for Gate-all-around (GAA) Device Development and Manufacturing
X. Gu, P. Hsu, Y.H. Kim, A. Mani, P. Kirby, Thermo Fisher Scientific, US |
| 2:20 | CHIPS Act Semiconductor Metrology Needs for R&D
D. Henshall, V. Zhirnov, T. Younkin, Semiconductor Research Corporation (SRC), US |
| 2:45 | Break
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| 2:55 | Surface and subsurface quantitative mechanical property measurements by contact resonance atomic force microscopy on low-k dielectric structures
G. Stan, C.V. Ciobanu, S.W. King, National Institute of Standards and Technology, US |
| 3:15 | Analysis of buried interfaces for device technology by soft and hard X-ray photoemission
K. Artyushkova, J. Mann, S. Zaccarine, Physical Electronics, US |
| 3:35 | Evaluating the Impact of Defects, Interfaces and Boundaries on Thermal Transport in 2D Materials Using a Novel Opto-Thermal Metrology Technique with Sub-Micron Resolution
B.M. Foley, A.H. Jones, J.T. Gaskins, P.E. Hopkins, Laser Thermal Inc, US |
| 3:55 | Silicon Dopant Quantification in Atom Probe Tomography
K. DeRocher, M. McLean, F. Meisenkothen, National Institute of Standards and Technology, US |
| Wednesday June 21 |
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| 9:00 | CHIPS: Advances in Packaging for New Chips Innovation | National Harbor 6 |
| Session chair: Joe Kline, National Institute of Standards and Technology, US |
| 9:00 | Novel, Robust Anisotropic Conductive Epoxy Technology for Advanced Semiconductor Packaging Applications
M. Ramkumar, SunRay Scientific Inc., US |
| 9:20 | What’s Missing in Your Cure Kinetics Model for Advanced Epoxy Molding Compounds?
R. Tao, S.P. Phansalkar, C. Kim, A.M. Forster, B. Han, National Institute of Standards and Technology, US |
| 9:40 | Enabling a circular economy of semiconductor process gases through Metal-Organic Frameworks (MOFs)
M.H. Weston, NuMat Technologies, US |
| 10:00 | X-ray Metrology for Semiconductor Nanostructures
J. Kline, National Institute of Standards and Technology,, US |
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